Integrated circuits include discrete devices, such as transistors, and interconnects for electrically connecting the discrete devices to each other. A typical transistor has a source region, a drain region and a gate electrode, which are disposed on a semiconductor substrate. The source and drain regions are spaced apart from each other in an active region of the semiconductor substrate. The gate electrode is disposed between the source region and the drain region and insulated from the active region.
Recently, as semiconductor devices have become more highly integrated, techniques have been developed that involve burying a gate electrode in a gate trench crossing the active region. A memory device, such as a dynamic random access memory (DRAM), typically has a plurality of cell transistors disposed in a cell array region and p-channel metal oxide semiconductor (pMOS) transistors and n-channel metal oxide semiconductor (nMOS) transistors disposed in a peripheral circuit region. The cell transistors are disposed at predetermined intervals in the cell array region. Gate electrodes of the cell transistors are connected to a word line.
A conventional technique for forming a buried word line involves burying the word line at a lower level than a top surface of the active region. For example, a semiconductor device having a buried word line is disclosed in U.S. Pat. No. 6,770,535 B2 entitled to “Semiconductor Integrated Circuit Device and Process for Manufacturing the Same” by Yamada et al.
Planar transistors such as high-voltage transistors may be disposed in the peripheral circuit region. Gate electrodes of the planar transistors may be disposed at a higher level than the active region. In addition, a plurality of gate lines may be formed at the same level as the gate electrodes.
However, the buried word line typically must be electrically connected to a gate line of the peripheral circuit region corresponding thereto. A technique for electrically connecting the buried word line with the gate line using a bypass interconnect and a contact plug has been developed. According to the technique using a bypass interconnect and a contact plug, a first interlayer insulating layer covering the buried word line and the gate line is formed, the bypass interconnect is disposed on the first interlayer insulating layer, and the contact plug penetrating the first interlayer insulating layer is used.
Other interconnects crossing between the buried word line and the gate line may be disposed on the first interlayer insulating layer. In order to electrically connect the buried word line with the gate line, a second interlayer insulating layer is formed on the first interlayer insulating layer, the bypass interconnect is disposed on the second interlayer insulating layer, and a contact plug penetrating the first and second interlayer insulating layers is used. The contact plug may difficult to form, and a signal transmission path may be lengthened. Consequently, a technique using a bypass interconnect and a contact plug may not provide an advantageous structure for high integration, and may degrade electrical characteristics and reliability.